[IEEE 2010 23rd International Conference on VLSI Design: concurrently with the 9th International Conference on Embedded Systems Design (VLSID) - Bangalore, India (2010.01.3-2010.01.7)] 2010 23rd International Conference on VLSI Design - 4 GHz 130nm Low Voltage PLL Based on Self Biased Technique
Viswanathan, Biju, Viswam, Vijay, R, Kulanthaivelu, Vettickatt, Joseph J., S.R, Ramya Nair, Chandran, Lekshmi S.Рік:
2010
Мова:
english
DOI:
10.1109/vlsi.design.2010.21
Файл:
PDF, 287 KB
english, 2010
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