Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure
Meng, Lingkuan, He, Xiaobin, Li, Chunlong, Li, Junjie, Hong, Peizhen, Li, Junfeng, Zhao, Chao, Yan, JiangТом:
13
Мова:
english
Журнал:
Journal of Micro/Nanolithography, MEMS, and MOEMS
DOI:
10.1117/1.jmm.13.3.033010
Date:
August, 2014
Файл:
PDF, 5.11 MB
english, 2014