[IEEE 2017 IEEE International Solid- State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2017.2.5-2017.2.9)] 2017 IEEE International Solid-State Circuits Conference (ISSCC) - 23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture
Rho, Kwangmyoung, Tsuchida, Kenji, Kim, Dongkeun, Shirai, Yutaka, Bae, Jihyae, Inaba, Tsuneo, Noro, Hiromi, Moon, Hyunin, Chung, Sungwoong, Sunouchi, Kazumasa, Park, Jinwon, Park, Kiseon, Yamamoto, AkРік:
2017
Мова:
english
DOI:
10.1109/ISSCC.2017.7870428
Файл:
PDF, 1.45 MB
english, 2017
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